Capacitors are one type of component commonly used in the fabrication of integrated circuits, for example in DRAM circuitry. A capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric region. As integrated circuitry density has increased, there is a continuing challenge to maintain sufficiently high storage capacitance despite typical decreasing capacitor area. The increase in density of integrated circuitry has typically resulted in greater reduction in the horizontal dimension of capacitors as compared to the vertical dimension. In many instances, the vertical dimension of capacitors has increased.
One manner of fabricating capacitors is to initially form an insulative material within which a capacitor storage node electrode is formed. For example, an array of capacitor electrode openings for individual capacitors may be fabricated in such insulative capacitor electrode-forming material, with an example insulative electrode-forming material being silicon dioxide doped with one or both of phosphorus and boron. The capacitor electrode openings may be formed by etching. It can be difficult to etch the capacitor electrode openings within the insulative material, particularly where the openings are deep.
Further and regardless, it is often desirable to etch away most if not all of the capacitor electrode-forming material after individual capacitor electrodes have been formed within the openings. Such enables outer sidewall surfaces of the electrodes to provide increased area and thereby increased capacitance for the capacitors being formed. However, the capacitor electrodes formed in deep openings are often correspondingly much taller than they are wide. This can lead to toppling of the capacitor electrodes, either during the etch to expose the outer sidewalls surfaces, during transport of the substrate, and/or during deposition of the capacitor dielectric layer or outer capacitor electrode layer. Our U.S. Pat. No. 6,667,502 teaches the provision of a brace or retaining structure intended to alleviate such toppling. Other aspects associated in the formation of a plurality of capacitors, some of which include bracing structures, are also disclosed and are:
U.S. Published Application No. 2005/0051822;
U.S. Published Application No. 2005/0054159;
U.S. Published Application No. 2005/0158949;
U.S. Published Application No. 2005/0287780;
U.S. Published Application No. 2006/0014344;
U.S. Published Application No. 2006/0051918;
U.S. Published Application No. 2006/0046420;
U.S. Published Application No. 2006/0121672;
U.S. Published Application No. 2006/0211211;
U.S. Published Application No. 2006/0263968;
U.S. Published Application No. 2006/0261440;
U.S. Published Application No. 2007/0032014;
U.S. Published Application No. 2006/0063344;
U.S. Published Application No. 2006/0063345;
Fabrication of capacitors in memory circuitry may form an array of capacitors within a capacitor array area. Control or other circuitry area is often displaced from the capacitor array area, with the substrate including an intervening area between the capacitor array area and the control or other circuitry area. In some instances, a trench is formed in the intervening area between the capacitor array area and the other circuitry area. Such trench can be formed commensurate with the fabrication of the openings within the capacitor array area within which the isolated capacitor electrodes will be received.
When etching the insulative electrode-forming material within which the capacitor electrodes are received to expose outer sidewall surfaces thereof, it is often desired that none of the insulative material within the other circuitry area be etched. One prior art method restricts such by masking the peripheral circuitry area. Specifically, a silicon nitride layer may be formed over the predominantly insulative material within which the capacitor electrodes are formed. The conductive material deposited to form the capacitor electrodes within the electrode openings also deposits and lines the trench between the capacitor array area and the peripheral circuitry area. One example conductive material is titanium nitride. The titanium nitride is polished back at least to the silicon nitride layer, thereby forming isolated container-shaped structures within individual capacitor electrode openings in the array area and within the trench. Accordingly, the sidewalls and bottom of the trench are covered or masked with titanium nitride, whereas the top or elevationally outermost surface of the peripheral or other circuitry area is covered with silicon nitride.
Etch access openings are then formed at spaced intervals within the silicon nitride within the capacitor array area to expose the insulative capacitor electrode-forming material therebeneath. Elevationally outermost surfaces of the peripheral circuitry area are typically kept entirely masked with the silicon nitride layer. When the insulative capacitor electrode-forming material comprises phosphorus and/or boron doped silicon dioxide, one example aqueous etching chemistry utilized to etch such highly selectively to titanium nitride and to silicon nitride is an aqueous HF solution. Such desirably results in exposure of the outer sidewalls of the individual capacitor electrodes while the peripheral insulative material remains masked from such etching by the overlying silicon nitride layer and from the titanium nitride within the peripheral trench.
Titanium nitride from which the capacitor electrodes are formed and which masks the sidewalls of the peripheral trench might be deposited in a manner which produces cracks or pinholes that extend laterally therethrough. This is not particularly problematic within the capacitor array area as it is desired that the insulative material be removed from both the inner and outer lateral sidewalls of the capacitor electrodes. Passage of liquid etchant through any cracks or pinholes within the array area does not defeat this purpose. However, cracks or pinholes in the titanium nitride layer protecting the lateral sidewalls of the peripheral circuitry insulative material can be problematic. Specifically, etchant seeping therethrough can cause etching voids or pockets to form laterally within the peripheral circuitry insulative material. These can later create fatal contact-to-contact shorts in the peripheral circuitry area when conductive vertical contacts are formed therein.
One existing solution to such problem is to deposit a very thin polysilicon layer to line internal portions of the capacitor electrodes and against the titanium nitride layer which laterally covers the insulative material of the peripheral circuitry area. Polysilicon is highly resistant to etch by HF. Such will shield any pinholes, thereby precluding HF or other etchants from seeping therethrough and undesirably etching the peripheral circuitry area insulative material.
Polysilicon is usually undesired subsequently, and is therefore removed. Accordingly, after etching back the insulative material to expose the outer sidewalls of the capacitor electrodes, a dedicated wet etch is conducted to highly selectively remove the polysilicon relative to undoped silicon dioxide, the titanium nitride, and the silicon nitride. Prior to this, a separate dedicated wet etch is conducted to remove an undesired native oxide which forms over the polysilicon.
Regardless of whether pinholes or cracks are formed in the capacitor electrode material, the material is often received against the silicon nitride, or other material, received over the insulative electrode-forming material. Such creates an interface or seam through which liquid etchant can seep which may undesirably cause etching of the insulative electrode-forming material in the periphery.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.